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HV257 32-Channel High Voltage Sample and Hold Amplifier Array
Features
32 independent high voltage amplifiers 300V operating voltage 295V output voltage 2.2V/s typical output slew rate Adjustable output current source limit Adjustable output current sink limit Internal closed loop gain of 72V/V 12M feedback impedance Layout ideal for die applications
General Description
The Supertex HV257 is a 32 channel high voltage sample and hold amplifier array integrated circuit. It operates on a single high voltage supply, up to 300V, and two low voltage supplies, VDD and VNN. All 32 sample and hold circuits share a common analog input, VSIG. The individual sample and hold circuits are selected by a 5 to 32 logic decoder. The sampled voltage on the holding capacitor is buffered by a low voltage amplifier and amplified by a high voltage amplifier with a closed loop gain of 72V/V. The internal closed loop gain is set for an input voltage range of 0V to 4.096V. The input voltage can be up to 5.0V but the output will saturate. The maximum output voltage swing is 5V below the VPP high voltage supply. The outputs can drive capacitive loads of up to 3000pF. The maximum output source and sink current can be adjusted by using two external resistors. An external RSOURCE resistor controls the maximum sourcing current, and an external RSINK resistor controls the maximum sinking current. The current limit is approximated 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low voltage silicon junction diode is made available to help monitor the die temperature.
Applications
MEMS (microelectromechanical systems) driver Piezoelectric transducer driver Optical crosspoint switches (using MEMS technology)
Typical Application Circuit
Supertex HV257
DAC VSIG Low Voltage Power Supply
High Voltage Power Supply HVOUT0 HVOUT1 HVOUT2 HVOUT3
x y y x
Micro Processor
A0 A1 A2 A3 A4 EN DGND 32 Low Voltage Channel Select Sample and Hold High Voltage OpAmp Array
MEMS Array HVOUT30 HVOUT31
RSOURCE RSINK AGND VNN
HV257
Absolute Maximum Ratings
VPP, High voltage supply AVDD, Analog low voltage positive supply DVDD, Digital low voltage positive supply AVNN, Analog low voltage negative supply DVNN, Digital low voltage negative supply Logic input voltage VSIG, Analog input signal SRVPP, VPP ramp up/down Storage temperature range Maximum junction temperature 310V 8.0V 8.0V -7.0V -7.0V -0.5V to DVDD 0V to 6.0V TBDV/usec -65C to 150C 150C
Device HV257
Package Options 100 Lead MQFP HV257FG HV257FG-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Operating Conditions
Symbol
VPP VDD VNN IPP IDD INN TJ
Parameter
High voltage positive supply Low voltage positive supply Low voltage negative supply VPP supply current VDD supply current VNN supply current Operating temperature range
Min
125 6.0 -4.5 -6.0 -10
Typ
-
Max
300 7.5 -6.5 0.8 5.0 85
Units
V V V mA mA mA C
Conditions
------VPP = 300V, All HVOUT = 0V No load VDD = 6.0V to 7.5V VNN = -4.5V to -6.5V ---
Electrical Characteristics (over operating conditions, unless otherwise specified)
High Voltage Amplifier Symbol
HVOUT VINOS SR BW AO AV RFB CLOAD ISOURCE ISINK RSOURCE RSINK CTDC PSRR
Parameter
HVOUT voltage swing Input offset HVOUT slew rate rise HVOUT slew rate fall HVOUT -3dB channel bandwidth Open loop gain Closed loop gain Feedback resistance from HVOUT to ground HVOUTt capacitive load HVOUT sourcing current limiting range HVOUT sinking current limiting range External resistance range for setting maximum current source External resistance range for setting maximum current sink DC channel to channel crosstalk Power supply rejection ratio for VPP, VDD, VNN
Min
0 70 68.4 9.6 0 50 50 25 25 -80 -40
Typ
2.2 2.0 4.0 100 72 12 -
Max
VPP-5 50 75.6 3000 500 500 250 250 -
Units
V mV V/s V/s KHz dB V/V M pF A A K K dB dB
Conditions
--Input referred No Load No Load VPP = 300V --------ISOURCE = 12.5V/RSOURCE ISINK = 12.5V/RSINK ---------
2
HV257
Electrical Characteristics (over operating conditions, unless otherwise specified)
Sample and Hold
Symbol tAQ VPED RSW CH VDROOP VSIG CSIG Parameter Acquisition time Pedestal voltage Sample and Hold Switch resistance Sample and Hold capacitor Voltage droop rate during hold time relative to input Input signal voltage range VSIG input capacitance Min 0 Typ 4.0 1.0 5.0 10 6.0 33 Max 12 5.0 Units s mV k pF V/s V pF Conditions --input referred ----output referred -----
Logic Decoder
Symbol tSU tH VIH VIL IIH IIL CIN Parameter Set-up time-address to enable Hold time-address to enable bar Input logic high voltage Input logic low voltage Input logic high current Input logic low current Logic input capacitance Min 75 75 2.4 0 -1.0 Typ Max VDD 1.2 1.0 15 Units ns ns V V A A pF Conditions --------VIL = VDD VIL = 0V ---
Decoder Truth Table
A4 L L L L A3 L L L L A2 L L L L A1 L L H H A0 L H L H EN H H H H Selected S/H 0 1 2 3
Sample and Hold Timing
tSU tH
A0-A4 EN
Hold Sample tR/F Hold Step (Vpedestal ) Hold
HVOpamp
H H X H H X H H X H H X L H X H H L 30 31 All Open
Acquisition Window
Temperature Diode
Symbol PIV VF IF TC Parameter Peak inverse voltage Forward diode drop Forward diode current VF temperature coefficient Min Typ 0.6 -2.2 Max 5.0 100 Units V V A mV/C Conditions cathode to anode IF = 100A, anode to cathode at TA = 25C anode to cathode anode to cathode
3
HV257
Block Diagram
BYP-VPP BYP-AVDD BYP-AVNN Anode Cathode
VPP AVDD AVNN DVDD DVNN VSIG Bias Circuit
To internal VPP bus To internal analog VDD bus To internal analog VNN bus To internal digital VDD bus To internal digital VNN bus + Q1 AVNN S/H -0 R 5 to 32 Decoder + AVDD VPP + HVOUT1 AVNN 71R R Q31 S/H -1 AVNN AVDD To all HVOUT amplifiers + HVOUT Current Source Limiting HVOUT Current Sink Limiting VPP HVOUT31 AVNN 71R R + AVNN S/H - 31 To all HVOUT amplifiers
4
AVDD VPP + HVOUT0 AVNN 71R -
DVDD Q0
A0 A1 A2 A3 A4
EN DGND
AGND
RSOURCE
RSINK
-
CH
-
CH
-
CH
HV257
Power Up/Down Issues
External Diode Protection
The device can be damaged due to improper power up / down sequence. To prevent damage, please follow the acceptable power up / down sequences, and add two external diodes as shown in the diagram on the right. The first diode is a high voltage diode across VPP and VDD , where the anode of the diode is connected to VDD and the cathode of the diode is connected to VPP. Any low current, high voltage diode, such as a 1N4004, will be adequate. The second diode is a Schottky diode across VNN and DGND , where the anode of the Schottky diode is connected to VNN , and the cathode is connected to DGND. Any low current Schottky diode such as a 1N5817 will be adequate.
External Diode Protection Connection VDD
1N4004 or similar
VPP
VNN
1N5817 or similar
DGND
Suggested Power Up/Down Sequence
The HV257 needs all power supplies to be fully up and all channels refreshed with VSIG = 0V to force all high voltage outputs to 0V. Before that time, the high voltage outputs may have temporary voltage excursions above or below Gnd level depending on selected power up sequence. To minimize the excursions: 1. The VDD and VNN power supplies should be applied at the same time (or within a few nanoseconds). 2. All channels should be continuously refreshed with VSIG = 0V, just before, and while the VPP is ramping up. Suggested VPP ramp up speed should be 10msec or longer and ramp down to be 1msec or longer.
Acceptable Power Up Sequences
The HV257 can be powered up with any of the following sequences listed below. 1) VPP 2) VNN 3) VDD 4) Inputs and Anode 1) VNN 2) VDD 3) VPP 4) Inputs and Anode 1) VDD & VNN 2) Inputs 3) VPP 4) Anode
Acceptable Power Down Sequences
The HV257 can be powered down with any of the following sequences listed below. 1) Inputs and Anode 2) VDD 3) VNN 4) VPP 1) Inputs and Anode 2) VPP 3) VDD 4) VNN 1) Anode 2) VPP 3) Inputs 4) VNN & VDD
Recommended Power Up/Down Timing
A0 - A4 EN
300V
0
1
2 31
0
0
1
2
VPP VDD VNN VSIG HVOUT
Gnd +/- V offset X 72
0V
6.5V 0V 0V -5.5V
0V 0V
HVOUT Level at Power UP
VPP VDD VNN
Power Up Sequence
VDD Before VNN
0V
VNN Before VDD
VPP VDD VNN
0V
6.5V 0V
6.5V 0V
0V -5.5V
0V -5.5V
HVOUT
0V -5.5V
HVOUT
6.5V 0V
5
HV257
RSINK / RSOURCE
The VDD_BYP ,VDD_BYP ,and VNN_BYP pins are internal. high impedance current. mirror gate nodes, brought out to mantain stable opamp biasing currents in noisy power supply environments. 0.1uF/25V bypass capacitors, added from VPP_BYP pin to VPP , from VDD_BYP pin to VDD , and from VNN_BYP to VNN,will force the high impedance gate
VPP BYP _VPP Cap 0.1uF / 25V BYP _VPP BYP _VDD BYP _VDD Cap 0.1uF / 25V VDD BYP _VNN BYP _VNN Cap 0.1uF / 25V VNN Current limit Set by RSINK Current limit
nodes to follow fluctuation of power lines. The expected voltages at the VDD_BYP, and VNN_BYP pins are typically 1.5 volts from their respectful power supply. The expected voltage at VPP_BYP is typically 3V below VPP.
Set by RSOURCE To internal biasing HVOUT0 HVOUT31 HVOpamp
HVOpamp
Ground Isolation (AGND/DGND Isolation)
It is important that the AGND pin is connected to a clean ground. The hold capacitors are internally connected to the AGND, and any ground noise will directly couple to the high voltage outputs (with a gain of 72). The analog and digital ground traces on the PCB should be physically separated to reduce digital switching noise degrading the signal to noise performance.
DGND C2 DVDD DAC C3 DVNN
EN, A0 -A4 External bypass caps: C1 = 0.1F / 500V C2, C3, C4, C5 = 0.1F / 25V
VSIG
Sample switch
LVOpamp
HVOpamp
HVOUT
C_hold 10pF AVNN C4 C5 C6 AGND1 (pins 89, 43) Single star GND AVDD
C_comp
1R VPP 71R C1
C_comp
AGND2 (pin 39)
6
HV257
Typical Characteristics
ISINK vs RSINK
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 600
ISOURCE vs RSOURCE
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 600
500
500
ISOURCE (A)
max
400
400
ISINK (A)
300
300
200
200
100
100
max min
min
0 25k 150k 250k
0
25k
150k
250k
RSINK (K)
RSOURCE (K)
Temperature Diode vs Temperature
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
Acquisition Window
("one RC" response to one volt input step)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 120
700
-10OC max
100
One RC (nsec)
80
+85OC +25OC -10OC
600 max
min
25OC
Vf (mV)
60
min 500 max min 400
85OC
40
20
300
0
1A
20A
40A
60A
80A
100A
1
2
4
VSIG Level (V)
Diode Biasing Current (A)
HVOUT Charge Injection vs VSIG
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
HVOUT Droop
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
3
40
2
20
HVOUT (mV)
HVOUT (V/sec)
1
0
-20
0
25OC
-40 0v 1v 2v 3v 4v
-1
85OC -10OC
VSIG Level (V)
-2 0 150 280
HVOUT Level (V)
7
HV257
Typical Characteristics (cont.)
VPP PSSR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 -40
3.5 3.0 2.5 2.0
Input Offset vs VIN and Temperature
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
VPP PSSR (dB)
-30 -20 -10 0 10 100 1k 10k 100k 1M
HVOUT (mV)
1.5
Offset at -10OC Offset at 25OC Offset at 85OC
-2.0 -2.5 -3.0
Frequency (Hz)
VDD PSSR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25 C)
O
-3.5 -4.0 -4.5
-50 -40
1
2
3
VDD PSSR (dB)
VIN (Volts)
-30 -20
73.97
Gain vs VIN
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC ) 73.96 73.95
-10 0
HVOUT (V)
10
100
1k
10
100
1M
73.94 73.93 72.74 72.73 72.72 72.71 72.70 72.69
1 2 3
Frequency (Hz)
VNN PSSR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 -40
VNN PSSR (dB)
VIN (Volts)
-30 -20 -10 0 10 100 1k 10k 100k 1M
HVOUT Drift
HV257DFG-5037047 Q3 Dev # 3, Channel 16 (VPP = 300V, VDD = 6.5V, VNN = -5V, VSIG=1V, TA = 25OC) 73.03 73.028 73.026
HVOUT (V)
Frequency
73.024 73.022 73.02 73.018 73.016 73.014
0
Time (hours)
8
8
HV257
Pad Configuration (not drawn to scale)
Byp-AVDD Byp-AVNN
Do Not Bond. For testing only Anode Cathode RSINK RSOURCE BYP-VPP VPP HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HVOUT0 VPP
AGND VSIG
DGND
DVNN
DVDD
AVNN AVNN AGND
AVDD
A4 A3 A2 A1 A0 EN
Do Not Bond. Leave Floating.
AVDD
AGND
DVNN
DVDD
9
HV257
Pad Coordinates
Chip size: 17160m x 5830m Center of die is (0,0)
10
HV257
Pin Description
Pin # 33,100 99 42,91 93 40,94 92 45, 87 44, 88 86 39, 43, 89 81-85 80 90 98 97 95 96 1-32 34-38, 41, 46-79 Function VPP BYP-VPP AVDD BYP-AVDD AVNN BYP-AVNN DVDD DVNN DGND AGND A0 to A4 EN VSIG RSOURCE RSINK Anode Cathode HVOUT0 to VOUT31 NC Description High voltage positive supply. There are two pads. For additional VPP decoupling capacitor. Analog low voltage positive supply. This should be at the same potential as DVDD. There are two pads. For additional AVDD decoupling capacitor. Analog low voltage negative supply. This should be at the same potential as DVNN. There are two pads. For additional AVNN decoupling capacitor. Digital low voltage positive supply. This should be at the same potential as AVDD. There are two pads. Digital low voltage negative supply. This should be at the same potential as AVNN. There are two pads. Digital ground. Analog Ground. There are three pads. They need to be externally connected together. Decoder logic input. Addressed channel will close the sample and hold switch. Sample and hold switches for unaddressed channels are kept open. Active logic high input. Logic low will keep sample and hold switches open. Common input signal for all 32 sample and hold circuits. External resistor from RSOURCE to VNN sets output current sourcing limit. Current limit is approximately 12.5V divided by RSOURCE resistor value. External resistor from RSINK to VNN sets output current sinking limit. Current limit is approximately 12.5V divided by RSINK resistor value. Anode side of a low voltage silicon diode that can be used to monitor die temperature. Cathode side of a low voltage silicon diode that can be used to monitor die temperature. Amplifier outputs. No Connect
11
HV257
Pin Layout
100 1 81 80
100 Lead MQFP (top view)
30 31 50
51
Pin Configuration
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Function HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HVOUT0 VPP NC NC NC NC NC AGND AVNN NC AVDD AGND DVNN DVDD NC NC NC NC NC Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function NC NC NC NC EN A0 A1 A2 A3 A4 DGND DVDD DVNN AGND VSIG AVDD BYP-AVNN BYP-AVDD AVNN Anode Cathode RSINK RSOURCE BYP-VPP VPP
Note: NC = No Connect
12
HV257
100-Lead MQFP Package Outline (FG)
20x14mm body, 3.15mm height (max.), 0.65mm pitch, 3.2mm footprint
D D1
E
Note 1 (Index Area E1/4 x D1/4)
1
E1
L2
100
Gauge Plane Seating Plane
L L1
1
e
b
Top View View B
A A2 A1
Seating Plane
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
Drawings not to scale.
A 2.50 3.15
A1 0.00 0.25
A2 2.50 2.70 2.90
b 0.22 0.40
D 22.95 23.20 23.45
D1 19.80 20.00 20.20
E 16.95 17.20 17.45
E1 13.90 14.00 14.20
e 0.65 BSC
L 0.73 0.88 1.03
L1 1.60 REF
L2 0.25 BSC
0
O
1 5O 16O
7O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
Doc.# DSFP-HV257 B121106
13

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